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2.5v lvds 1:6 clock buffer terabuffer? ii idt5t9306 idt ? / ics ? lvds clock buffer terabuffer? ii 1 idt5t9306 rev. b april 15, 2008 gl g pd a1 a1 a2 a2 sel output control output control output control output control output control output control q2 q2 q1 q1 q3 q3 q4 q4 q5 q5 q6 q6 1 0 description: the idt5t9306 2.5v differential clock buffer is a user-selectable differential input to six lvds outputs. the fanout from a differential input to six lvds outputs reduces loading on the preceding driver and provides an efficient clock distribution network. the idt5t9306 can act as a translator from a differential hstl, ehstl, lvepecl (2.5v), lvpecl (3.3v), cml, or lvds input to lvds outputs. a single-ended 3.3v / 2.5v lvttl input can also be used to translate to lvds outputs. the redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. selectable reference inputs are controlled by sel. the idt5t9306 outputs can be asynchronously enabled/disabled. when disabled, the outputs will drive to the value selected by the gl pin. multiple power and grounds reduce noise. features: ? guaranteed low skew < 25ps (max) ? very low duty cycle distortion < 125ps (max) ? high speed propagation delay < 1.75ns (max) ? additive phase jitter, rms 0.159ps (typical) @ 125mhz ? up to 1ghz operation ? selectable inputs ? hot insertable and over-voltage tolerant inputs ? 3.3v / 2.5v lvttl, hstl, ehstl, lvepecl (2.5v), lvpecl (3.3v), cml, or lvds input interface ? selectable differential inputs to six lvds outputs ? power-down mode ? 2.5v v dd ? available in vfqfpn package functional block diagram applications: ? clock distribution
idt ? / ics ? lvds clock buffer terabuffer? ii 2 idt5t9306 rev. b april 15, 2008 idt5t9306 2.5v lvds 1:6 clock buffer terabuffer? ii pin configuration 18 21 20 19 17 16 15 pd a 2 q 4 q 4 v dd a 2 v dd 14 13 8910 11 12 q 2 q 2 q 3 q 3 v d d g l v d d 27 26 25 24 23 22 28 v d d s e l q 6 q 6 q 5 q 5 n c 1 2 3 4 5 6 7 v dd g q 1 q 1 v dd a 1 a 1 gnd vfqfpn top view
idt ? / ics ? lvds clock buffer terabuffer? ii 3 idt5t9306 rev. b april 15, 2008 idt5t9306 2.5v lvds 1:6 clock buffer terabuffer? ii symbol d escription max unit v dd power supply voltage ?0.5 to +3.6 v v i input voltage ?0.5 to +3.6 v v o output voltage (2) ?0.5 to v dd +0.5 v t stg storage temperature ?65 to +150 c t j junction temperature 150 c absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. not to exceed 3.6v. symbol parameter min typ. max. unit c in input capacitance ?? 3pf capacitance (1) (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested symbol description min. typ. max. unit t a ambient operating temperature ?40 +25 +85 c v dd internal power supply voltage 2.3 2.5 2.7 v recommended operating range pin description symbol i/o type description a [1:2] i adjustable (1,4) clock input. a [1:2] is the "true" side of the differential clock input. a [1:2] i adjustable (1,4) complementary clock inputs. a [ 1:2] is the complementary side of a [1:2]. for lvttl single-ended operation, a [ 1:2] should be set to the desired toggle voltage for a [1:2] : 3.3v lvttl v ref = 1650mv 2.5v lvttl v ref = 1250mv g i lvttl gate control for differential outputs q 1 and q 1 through q 6 and q 6 . when g is low, the differential outputs are active. when g is high, the differential outputs are asynchronously driven to the level designated by gl (2) . gl i lvttl specifies output disable level. if high, "true" outputs disable high and "complementary" outputs disable low. if low, "true" outputs disable low and "complementary" outputs disable high. qn o lvds cl ock outputs q n o lvds com plementary clock outputs sel i lvttl reference clock select. when low, selects a 2 and a 2 . when high, selects a 1 and a 1 . pd i lvttl power-down control. shuts off entire chip. if low, the device goes into low power mode. inputs and outputs are disabled. bo th "true" and "complementary" outputs will pull to v dd . set high for normal operation. (3) v dd pwr power supply for the device core and inputs gnd pwr power supply return for all power n c no connect; recommended to connect to gnd notes: 1. inputs are capable of translating the following interface standards: single-ended 3.3v and 2.5v lvttl levels differential hstl and ehstl levels differential lvepecl (2.5v) and lvpecl (3.3v) levels differential lvds levels differential cml levels 2. because the gate controls are asynchronous, runt pulses are possible. it is the user's responsibility to either time the gat e control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 3. it is recommended that the outputs be disabled before entering power-down mode. it is also recommended that the outputs rema in disabled until the device completes power- up after asserting pd . 4. the user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.
idt ? / ics ? lvds clock buffer terabuffer? ii 4 idt5t9306 rev. b april 15, 2008 idt5t9306 2.5v lvds 1:6 clock buffer terabuffer? ii dc electrical characteristics over operating range for lvttl (1) symbol parameter test conditions min. typ. (2) max unit input characteristics i ih input high current v dd = 2.7v ? ? 5 a i il input low current v dd = 2.7v ? ? 5 v ik clamp diode voltage v dd = 2.3v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 ? +3.6 v v ih dc input high 1.7 ? ? v v il dc input low ? ? 0.7 v v thi dc input threshold crossing voltage ? v dd /2 ? v v ref single-ended reference voltage (3) 3.3v lvttl ? 1.65 ? v 2.5v lvttl ? 1.25 ? notes: 1. see recommended operating range table. 2. typical values are at v dd = 2.5v, +25c ambient. 3. for a [1:2] single-ended operation, a [1:2] is tied to a dc reference voltage. dc electrical characteristics over operating range for differential inputs (1) symbol parameter test conditions min. typ. (2) max unit input characteristics i ih input high current v dd = 2.7v ? ? 5 a i il input low current v dd = 2.7v ? ? 5 v ik clamp diode voltage v dd = 2.3v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 ? +3.6 v v dif dc differential voltage (3) 0.1 ? ? v v cm dc common mode input voltage (4) 0.05 ? v dd v notes: 1. see recommended operating range table. 2. typical values are at v dd = 2.5v, +25c ambient. 3. v dif specifies the minimum input differential voltage (v tr - v cp ) required for switching where v tr is the "true" input level and v cp is the "complement" input level. the dc differential voltage must be maintained to guarantee retaining the existing high or low input. the ac differential voltage must be achieved to guarantee switching to a new state. 4. v cm specifies the maximum allowable range of (v tr + v cp ) /2. dc electrical characteristics over recommended operating range for lvds (1) symbol parameter test conditions min. typ. (2) max unit output characteristics v ot (+) differential output voltage for the true binary state 247 ? 454 mv v ot (-) differential output voltage for the false binary state 247 ? 454 mv v ot change in v ot between complementary output states ? ? 50 mv v os output common mode voltage (offset voltage) 1.125 1.2 1.375 v v os change in v os between complementary output states ? ? 50 mv i os outputs short circuit current v out + and v out - = 0v ? 12 24 ma i osd differential outputs short circuit current v out + = v out -?612ma notes: 1. see recommended operating range table. 2. typical values are at v dd = 2.5v, t a = +25c ambient.
idt ? / ics ? lvds clock buffer terabuffer? ii 5 idt5t9306 rev. b april 15, 2008 idt5t9306 2.5v lvds 1:6 clock buffer terabuffer? ii differential input ac test conditions for ehstl symbol parameter value units v dif input signal swing (1) 1v v x differential input signal crossing point (2) 900 mv d h duty cycle 50 % v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 2v/ns notes: 1. the 1v peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (at e) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a 900mv crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate) envir onment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 2v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. differential input ac test conditions for hstl symbol parameter value units v dif input signal swing (1) 1v v x differential input signal crossing point (2) 750 mv d h duty cycle 50 % v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 2v/ns notes: 1. the 1v peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (at e) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a 750mv crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate) envir onment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 2v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. differential input ac test conditions for lvepecl (2.5v) and lvpecl (3.3v) symbol parameter value units v dif input signal swing (1) 732 mv v x differential input signal crossing point (2) lvepecl 1082 mv lvpecl 1880 d h duty cycle 50 % v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 2v/ns notes: 1. the 732mv peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ate) environment. this device meets the v dif (ac) specification under actual use conditions. 2. 1082mv lvepecl (2.5v) and 1880mv lvpecl (3.3v) crossing point levels are specified to allow consistent, repeatable results in an automatic test equipment (ate) environment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 2v/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
idt ? / ics ? lvds clock buffer terabuffer? ii 6 idt5t9306 rev. b april 15, 2008 idt5t9306 2.5v lvds 1:6 clock buffer terabuffer? ii differential input ac test conditions for lvds symbol parameter value units v dif input signal swing (1) 400 mv v x differential input signal crossing point (2) 1.2 v d h duty cycle 50 % v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 2v/ns notes: 1. the 400mv peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ate) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a 1.2v crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate) enviro nment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 2v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. power supply characteristics for lvds outputs (1) symbol parameter test conditions typ. max unit i ddq quiescent v dd power supply current v dd = max., all input clocks = low (2) ? 240 ma outputs enabled i tot total power v dd supply current v dd = 2.7v., f reference clock = 1ghz ? 250 ma i pd total power down supply current pd = low ? 5 ma notes: 1. these power consumption characteristics are for all the valid input interfaces and cover the worst case conditions. 2. the true input is held low and the complementary input is held high. ac differential input specifications (1) symbol parameter min. typ. max unit v dif ac differential voltage (2) 0.1 ? 3.6 v v ix differential input crosspoint voltage 0.05 ? v dd v v cm common mode input voltage range (3) 0.05 ? v dd v v in input voltage - 0.3 +3.6 v notes: 1. the output will not change state until the inputs have crossed and the minimum differential voltage range defined by v dif has been met or exceeded. 2. v dif specifies the minimum input voltage (v tr - v cp ) required for switching where v tr is the "true" input level and v cp is the "complement" input level. the ac differential voltage must be achieved to guarantee switching to a new state. 3. v cm specifies the maximum allowable range of (v tr + v cp ) /2.
idt ? / ics ? lvds clock buffer terabuffer? ii 7 idt5t9306 rev. b april 15, 2008 idt5t9306 2.5v lvds 1:6 clock buffer terabuffer? ii ac electrical characteristics over operating range (1,5) symbol parameter min. typ. max unit skew parameters t sk ( o ) same device output pin-to-pin skew (2) ? ? 25 ps t sk ( p ) pulse skew (3) ?? 125 ps t sk ( pp ) part-to-part skew (4) ?? 300 ps propagation delay t plh propagation delay a, a crosspoint to qn, qn crosspoint ? 1.25 1.75 ns t phl f o frequency range (6) ?? 1 ghz output gate enable/disable delay t pge output gate enable crossing v thi to qn/ qn crosspoint ?? 3.5 ns t pgd output gate disable crossing v thi to qn/ qn crosspoint driven to gl designated level ?? 3.5 ns power down timing t pwrdn pd crossing v thi to qn = v dd , qn = v dd ?? 100 s t pwrup output gate disable crossing v thi to qn/ qn driven to gl designated level ?? 100 s rms additive phase jitter rms additive phase jitter @ 25mhz (12khz ? 10mhz integration range) 0.541 ps t jit rms additive phase jitter @ 125mhz (12khz ? 20mhz integration range) 0.159 ps rms additive phase jitter @ 156.25mhz (12khz ? 20mhz integration range) 0.185 ps output rise/fall time t r /t f output rise/fall time (6) , (20% - 80%) 125 600 ps notes: 1. ac propagation measurements should not be taken within the first 100 cycles of startup. 2. skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions a nd load conditions on any one device. 3. skew measured is the difference between propagation delay times t phl and t plh of any differential output pair under identical input and output interfaces, transitions and load conditions on any one device. 4. skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devi ces, given identical transitions and load conditions at identical v dd levels and temperature. 5. all parameters are tested with a 50% input duty cycle. 6. guaranteed by design but not production tested.
idt ? / ics ? lvds clock buffer terabuffer? ii 8 idt5t9306 rev. b april 15, 2008 idt5t9306 2.5v lvds 1:6 clock buffer terabuffer? ii t plh t phl t sk(o) t sk(o) qn - qn qm - qm + v dif v dif = 0 - v dif + v dif v dif = 0 - v dif a [1:2] - a [1:2] + v dif v dif = 0 - v dif 1/fo differential ac timing waveforms output propagation and skew waveforms notes: 1. pulse skew is calculated using the following expression: t sk ( p ) = | t phl - t plh | note that the t phl and t plh shown above are not valid measurements for this calculation because they are not taken from the same pulse. 2. ac propagation measurements should not be taken within the first 100 cycles of startup.
idt ? / ics ? lvds clock buffer terabuffer? ii 9 idt5t9306 rev. b april 15, 2008 idt5t9306 2.5v lvds 1:6 clock buffer terabuffer? ii power down timing notes: 1. it is recommended that outputs be disabled before entering power-down mode. it is also recommended that the outputs remain d isabled until the device completes power-up after asserting pd . 2. the power down timing diagram assumes that gl is high. 3. it should be noted that during power-down mode, the outputs are both pulled to v dd . in the power down timing diagram this is shown when qn- qn goes to v dif = 0. a 1 - a 1 g v thi v ih v il qn - qn +v dif v dif =0 - v dif +v dif v dif =0 -v dif +v dif v dif =0 -v dif pd a 2 - a 2 v thi v ih v il differential gate disable/enable showing runt pulse generation note: 1. as shown, it is possible to generate runt pulses on gate disable and enable of the outputs. it is the user's responsibility to time the g signal to avoid this problem. t plh gl g qn - qn t pgd t pge v ih v thi v il v ih v thi v il + v dif v dif = 0 - v dif a [1:2] - a [1:2] + v dif v dif = 0 - v dif
idt ? / ics ? lvds clock buffer terabuffer? ii 10 idt5t9306 rev. b april 15, 2008 idt5t9306 2.5v lvds 1:6 clock buffer terabuffer? ii test circuits and conditions v dd /2 d.u.t. a a pulse generator ~50 transmission line ~50 transmission line v in v in -v dd /2 scope 50 50 test circuit for differential input differential input test conditions symbol v dd = 2.5v 0.2v unit v thi crossing of a and a v
idt ? / ics ? lvds clock buffer terabuffer? ii 11 idt5t9306 rev. b april 15, 2008 idt5t9306 2.5v lvds 1:6 clock buffer terabuffer? ii v dd d.u.t. a a qn qn pulse generator r l r l v os v od v dd /2 d.u.t. a a qn qn pulse generator 50 50 z = 50 z = 50 scope c l -v dd /2 c l test circuit for dc outputs and power down tests test circuit for propagation, skew, and gate enable/disable timing notes: 1. specifications only apply to "normal operations" test condition. the t ia /e ia specification load is for reference only. 2. the scope inputs are assumed to have a 2pf load to ground. t ia /e ia - 644 specifies 5pf between the output pair. with c l = 8pf, this gives the test circuit appropriate 5pf equivalent load. lvds output test condition symbol v dd = 2.5v 0.2v unit c l 0 (1) pf 8 (1,2) r l 50
idt ? / ics ? lvds clock buffer terabuffer? ii 12 idt5t9306 rev. b april 15, 2008 idt5t9306 2.5v lvds 1:6 clock buffer terabuffer? ii recommended landing pattern nl 28 pin note: all dimensions are in millimeters.
idt ? / ics ? lvds clock buffer terabuffer? ii 13 idt5t9306 rev. b april 15, 2008 idt5t9306 2.5v lvds 1:6 clock buffer terabuffer? ii july 23, 2002 datasheet creation october 8, 2002 page 1, entire page changed; page 2, both diagrams; page 3, pin description and notes; page 4, dc cha. for lvpec l and differential input tables; page 6, dc cha. and power supply tables; page 7, entire page; page 9, added note 3; page 10, entire page; page 10, entire page; page 11, entire page; page 12, ordering info; added 3 new pages (10 thru 12) of diagrams. october 10, 2002 page 1, entire page changed; page 2, both diagrams; page 3, pin description and notes; page 7, ac cha. table; p age 8, added new lvpecl table; page 10, removed input clock switching diagram; page 11, deleted entire page; page 12, changed power down timing; page 15, ordering info. october 24, 2002 page 2, added note 1 to tqfp top view text; page3, aded note 4 to pin description; page 4, replaced "compliant devices must meet" with the text "this device meets" in four instances; page 5, differential input table, note 1, changed 1v to 732mv and replaced "compliant devices must meet" with the text "this device meets"; page 6, dc electrical table, vdif row, changed min. value to 0.1, and under differential input table replaced "compliant devices must meet" with the text "this device meets" page 7, power supply table, replaced ((tbd)) with 800mhz, and under ac electrical table, replaced ((tbd)) with 500; page 8, completely altered ac differential table; page 12, lvds output table, replaced ((tbd)) with 3. november 1, 2002 radical changes to entire document. december 12, 2002 radical changes to entire document, using 5t9316 as a base. december 16, 2002 throughout document, removed "differential" from title; page 7, power supply table, changed max values, change d f reference value; page 10, note 1, changed g x to g . may 8, 2003 page 2, corrected pinout diagram. august 7, 2003 page 1, features text, 3rd bullet, changed 2ns to 1.75ns, 4th bullet, changed 800mhz to 1ghz, and 7th bullet, add ed cml, on description, 3rd line, added cml to list; page 4, pin descr., note 1, added "differential cml levels", for description of pd row, replaced 2nd sentence with "both 'true' and 'complementary' output will pull to vdd"; page 5, dc... for differential inputs table, removed note 5 and changed vcm max. from 3.5 to vdd; page 7, power supply table, changed 800mhz to 1ghz; page 8, ac differential table, changed vix and vcm max specs from 3.5v to vdd, removed notes 4 and 5, and placed entire table on page 7, for ac elect. table, added notes 5 and 6, changed ((tbd)) to 300ps, tplh type to 1.25ns, and max from 2ns to 1.75ns, and changed fo max from 800mhz to 1ghz. october 2, 2003 page 1, features, 7th bullet, added "3.3v / 2,5v lvttl" to front, description, added to 1st paragraph "a single- ended 3.3v / 2.5v lvttl input can also be used to translate to lvds outputs."; page 4, pin description table, added large block of text to 2nd row, added "single-ended 3.3v and 2.5v lvttl levels" to note 1; page 5, dc for lvttl table, added vref row and note 3, for dc for lvds table, changed ios ratings from 5 typ, 7.5 max to 12 typ, 24 max, and changed iosd ratings from 5 typ, 7.5 max to 6 typ, 12 max; page 7, power supply table, changed ipd from 3 to 5. march 26, 2004 page 2, changed pin 22 to nc; page 3, changed pin 25 to nc; page 4, added nc row to pin description. june 22, 2004 removed tqfp package. october 26, 2004 inserted a page before ordering info and added landing pattern. october 27, 2004 added note to landing pattern. october 29, 2004 changed landing pattern diagram. march 9, 2005 page 6, switched iddq and itot values. october 23, 2007 page 7, added additive phase jitter, rms specs to the ac electrical characterisitcs table. april 15, 2008 page 7, added rise/fall time spec. to the ac electrical characteristics table.
idt5t9306 2.5v lvds 1:6 clock buffer terabuffer? ii innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt for tech support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. a ll other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ordering information idt xxxxx package device type 5t9306 2.5v 1:6 lvds clock buffer terabuffer? ii thermally enhanced plastic very fine pitch quad flat no lead package nl xx process x -40c to +85c (industrial) i

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